1. Field of the Invention
This invention relates to integrated semiconductor memory circuits and more particularly to memory circuits which employ capacitors for storing binary digits of information.
2. Description of the Prior Art
Integrated semiconductor memory circuits, particularly those employing cells which include essentially a storage capacitor and a switch, have achieved high memory cell densities. One of the simplest circuits for providing small memory cells is described in commonly assigned U.S. Pat. No. 3,387,286, filed July 14, 1967, by R. H. Dennard. Each of these cells employs a storage capacitor and a field effect transistor acting as a switch to selectively connect the capacitor to a bit/sense line. In also commonly assigned U.S. Pat. No. 3,811,076, by W. M. Smith, and U.S. Pat. No. 3,841,926 by R. H. Garnache and W. M. Smith, both filed Jan. 2, 1973, there is disclosed a one device field effect transistor memory cell of the type described in the above identified Dennard patent which is made to a small size by utilizing a layer of doped polycrystalline silicon separated by a dielectric medium disposed on the surface of a semiconductor substrate for forming a storage capacitor. These latter two patents also teach a process which uses very effectively a dual insulation layer of silicon dioxide and silicon nitride.
In commonly assigned copending application having Ser. No. 587,528, filed on June 16, 1975, by W. D. Pricer and J. E. Selleck there is described a memory array made of small cells which employ storage capacitors and bipolar transistors. In this latter array, which is word organized, each storage capacitor of these cells has simply one capacitor terminal connected to a separate bit/sense line while selected cells forming a word are simultaneously accessed by utilizing a word pulse for coupling to the other terminal of the storage capacitors of that word. By simultaneously accessing the other terminal of all storage capacitors of a particular word, isolation between cells of the word is not required.
In another commonly assigned application having Ser. No. 672,197, entitled "Capacitor Storage Memory", and filed on even date by W. D. Pricer, there is disclosed a capacitor memory produced in a unipolar technology which is provided with very small cells, each of which includes substantially only a storage capacitor having a bit/sense line connected to one terminal of the capacitor and a word line providing a coupling to the other terminal of the capacitor. In an embodiment of that invention, a direct current source of charges is produced at the surface of a semiconductor substrate and a plurality of inversion storage capacitors are formed also at the surface of the semiconductor substrate in a spaced apart relationship from the charge source. Voltage pulses representing binary digits are applied to one terminal of the capacitors and the other terminal of the capacitors is coupled to the direct current source of charges by the application of a word pulse to a word line.
In yet another commonly assigned application having Ser. No. 672,198, entitled "Injected Charge Capacitor Memory" and filed on even date by H. S. Lee, there is disclosed a random access capacitor memory which utilizes pulse charge injection for producing puddles or packets of charge representing binary digits.
IBM Technical Disclosure Bulletin, Vol. 18, No. 3, August 1975, pages 786 and 787, in an article entitled "Semiconductor Storage Circuit Utilizing Two Device Memory Cells" and U.S. Pat. No. 3,771,148, filed Mar. 31, 1972, teach the use of a pair of capacitors for storing complementary signals in a single cell.